CLKPOL=0, REV_VS=0, SWAP_SEL=0, PBSIZ=000, SCLKIDLE=0, END_SEL=0, ACDSEL=0, TFT=0, BPIX=000, FLMPOL=0, SCLKSEL=0, PIXPOL=0, OEPOL=0, COLOR=0, LPPOL=0
LCDC panel configuration register
| PCD | Pixel clock divider |
| SCLKSEL | LSCLK select 0 (0): Disable OE and LSCLK in TFT mode when no data output. 1 (1): Always enable LSCLK in TFT mode even if there is no data output. |
| ACD | Alternate crystal direction |
| ACDSEL | ACD clock source select 0 (0): Use FLM as a clock source for ACD count. 1 (1): Use LP/HSYNC as a clock source for ACD count. |
| REV_VS | Reverse vertical scan 0 (0): Vertical scan in normal direction. 1 (1): Vertical scan in reverse direction. |
| SWAP_SEL | Swap select 0 (0): 24 bpp, 18 bpp, 16 bpp, 12 bpp mode. 1 (1): 8 bpp, 4 bpp, 2 bpp, and 1 bpp mode. |
| END_SEL | Endian select 0 (0): Little Endian 1 (1): Big Endian |
| SCLKIDLE | LSCLK idle enable 0 (0): Disable LSCLK 1 (1): Enable LSCLK |
| OEPOL | Output enable polarity 0 (0): Active high 1 (1): Active low |
| CLKPOL | LCD shift clock polarity 0 (0): Active on negative edge of LSCLK. In TFT mode, active on positive edge of LSCLK. 1 (1): Active on positive edge of LSCLK. In TFT mode, active on negative edge of LSCLK. |
| LPPOL | Line pulse polarity 0 (0): Active high 1 (1): Active low |
| FLMPOL | First line marker polarity 0 (0): Active high 1 (1): Active low |
| PIXPOL | Pixel polarity 0 (0): Active high 1 (1): Active low |
| BPIX | Bits per pixel 0 (000): 1 bpp, FRC bypassed 1 (001): 2 bpp 2 (010): 4 bpp 3 (011): 8 bpp 4 (100): 12 bpp (16-bits of memory used) 5 (101): 16 bpp 6 (110): 18 bpp (32-bits of memory used) 7 (111): 24 bpp (32-bits of memory used) |
| PBSIZ | Panel bus width 0 (000): 1-bit 1 (001): 2-bit 2 (010): 4-bit 3 (011): 8-bit |
| COLOR | Interfaces to color display 0 (0): LCD panel is a Monochrome display. 1 (1): LCD panel is a Color display. |
| TFT | Interfaces to TFT display 0 (0): LCD panel is a passive display. 1 (1): LCD panel is an active display: “digital CRT” signal format, FRC is bypassed. |